The main goal of this Ariadna study was to determine the radiation hardness of potential future space processors. The AR0 test-chip was used to study the impact of SEUs and SETs on different versions of a hardened processor on UTBB-FDSOI 28nm technology, including DICE flip-flops, and three different hardening level of combinational logic.

Two chips especially designed to study the operation of complex circuits in ST Microelectronics 28 nm UTBB-FDSOI technology under radiation environments were developed and tested. The first test chip was designed for Single Event Transient (SET) pulse characterisation using (1) a Pulse Capture detector, (2) a Vernier detector, and (3) a Pulse Filter detector. To study SET event rate vs. clock frequency, a high-speed Circuit for Radiation Effects Self-Test chain with 4096 stages was embedded in the chip. The second chip was used to to study the impact of SEUs and SETs on complex circuitry, namely different customized variants of an ARM microprocessor. For this, five variants of the ARM- Cortex-M0 are implemented on the die. A reference M0 microprocessor variant is implemented with regular flip-flops and normal logic. A second variant is implemented using custom-designed DICE flip-flops. Three other variants are implemented with different levels of redundant logic.

Results:

• We measured the single event pulse width of the 28nm UTBB-FDSOI due to irradiation particles, and found the pulse widths of the SET pulses significantly smaller than those of bulk technologies with similar feature size.

• We noticed from the experiments that the error rate contribution from SET is at least one order of magnitude smaller than that of the SEU.

• The 28nm UTFDSOI has a relatively high total dose tolerance. It shows a small leakage increase below 300 krad(SiO2), and the circuit is functional up to 1Mrad (SiO2).

• Five ARM core processors have been developed on a single die and the test chip has passed functional testing.