Efficient Information-Preserving Image Compression for Space Applications EIPICSA

The objective of the activity is the full development and validation of a high throughput FPGA compressor IP core as well as the associated software decompressor, targeting future Earth Observation applications.

The proposed activity will focus on the implementation of the company?s compression technology for high-resolution Earth Observation systems. The tight coupling between the physical models of image acquisition and information theory has allowed the company?s technology to achieve outstanding performance in terms of compression ratio, throughput, power consumption and FPGA resource utilization. Besides the performance benefits, the lossless encoding allows it to be transparently integrated into existing systems and infrastructure, from TIFF files, Cloud Optimized Geo TIFF, or even at the network or storage level.;Because of the increasing resolutions of remote sensing missions (spatial, spectral, temporal and radiometric/dynamic range), data compression solutions are becoming an important cost-reducing technology.;The activity will take over from a previous activity executed in the frame of GSTP Element 1 (reference: G617-241TAdk) during which the VHDL implementation of the main compression component was produced and validated through simulation using drone captured images.;The proposed activity aims to further mature the technology aiming to validate the product?s performance in a system set-up including a camera assembly and a FPGA board. The main activities will include:1. Algorithm development (including new key pre-processingfunctions)2. Software implementation, notably for the decompressorproduct (including integer arithmetic for more precise SW/HWemulation)3. VHDL design and implementation4. Hardware integration (system including FPGA, RAM andcamera)5. System characterisation and test;The main development activities will include: Software development, a hardware definition phase, hardware architecture and detailed design, hardware layout and finally hardware validation and release.