In-Flight maintenance for System-on-Chip based computers

To define new services and operations for maintaining on-board System-on-Chip computers

On-board systems are on the verge making use of state-of-the art multi-core processors and FPGA technologies that encompass multiple functional blocks and features. The investigations on how to exploit such technologies was started in the three-ways TRP activities (T701-504ED, T702-502SW, T705-504EC) under the umbrella of Compact Reconfigurable Avionics. In such systems, the Software running on multiple-cores can be tightly coupled to functions implemented in the reconfigurable FPGA. The interactions between SW components and the corresponding HW functionality become exponentially more complex. Dynamic state management needs to be taken into account to guarantee that the HW reprogramming and SW update are orchestrated in a precise and timely controlled manner. ;The activity aims at covering all the aspects related to the update of the Software and FPGA on-board a spacecraft. ;This encompasses the following tasks: - Perform a system analysis for identifying future mission needs and constraints related to the HW and SW updates (e.g. availability of the system during the update, on-board storage, configuration management, authentication, etc.). - Identify the representative use cases allowing verifying the proposed approach. - Specification of the update process and software covering both Ground and Space segments compliant to ECSS-E-ST-70-41C (Telemetry and telecommand packet utilization). - Detailed design and implementation on a relevant hardware platform using state of the art space qualified processor and FPGA (potentially combined into a SoC). - Demonstration of the use cases and assessment of the results, identification of lessons learned. ;Software shall be delivered under an ESA Software Community Licence, so that any individuals or entities within ESA Member States can access to it and can provide update to the community of users.