New satellite designs entail more and more complex functionalities implemented in Field Programmable Gate Arrays (FPGA). Although Europe is far behind the US in the availability of powerful FPGAs, the first European reprogrammable radiation hard FPGAs offer the unique opportunity to develop new, larger capacity European ITAR-free FPGAs including the silicon parts, software hardware development and programming tools to be able to cover the big gap.

The library has already been defined in the Phase 1 TRP activity (KIPSAT). The present activity proposes the design, prototyping and testing of Standard Cell and Metal Customizable libraries, representing in total ~ 300 cells. Simulations shall be performed to demonstrate the cells performances and cells radiation hardness. Ageing shall also be taken into account by considering 20 years operational lifetime. The libraries test vehicles shall be manufactured and evaluated according the ECSS test procedures (temperature, radiation). The libraries shall also propose memory generators.

The NGMP architectural design is currently under way in TRP contract 22279. Early prototypes shall be manufactured by the end of 2010 in commercial Application Specific Integrated Circuit (ASIC) technology (eASIC, UMC, TSMC 90nm). The present activity starts with the functional validation of the early prototypes. With feedback from this validation and from other beta users, the NGMP design will be consolidated, and manufactured as an Engineering Model in the target space technology, the 65nm by STM, which is currently being developed under TRP and FP7 activities.

Performance of European processors for space applications have been increasing over the years, from the ERC32 (25MHz, current missions) to the single-core Leon2/3 (100MHz, upcoming missions) to the next generation processor (multicore, Leon4, future missions). Simulators are needed throughout the software, spacecraft and operations development. Simulator performance needs to keep the pace with the processors. Instruction set simulators for the ERC32 could keep up with real-time simulation of the overall spacecraft.

An ESA study is starting considering the system aspects of the use of the multi-core for our applications, and this study will define the final technical solutions. However, the trend seems to be towards the use of a hypervisor. If this is confirmed, there could be a convergence between the various hypervisors used for partitioning, for security and for multi-core. An environment for hypervisor could therefore be reused, which is the focus of the the proposed activity.