1) develop performant and representative emulators (in SW and/or HW) for future CPUs (NGMP Next Generation Multicore Processors)Intermediate objectives:2) consolidate Just-In-Time(JIT)/Dynamic-Tranlation/Block-oriented simulators of CPUs and demonstrate their improved performance for software3) Evolve FPGA-based hardware-in-the-loop emulators of Leon2/3 towards NGMP next generation multi core processors4) Characterise the emulators of Leon2/3 and future processors against benchmarks5)Use the concept of "software bus" of the on-board software reference architecture (which interface the application software to the basic software) in order to demonstrate its use for simulators of Basic Software to boost simulation speed beyond the performance of instruction set and JIT emulators6) Define , in relation with the on-board software reference architecture, the internal interfaces of Software Validation Facilities and Operational simulators to enable hardware suppliers to supply models of their HW that can be re-used by all simulator-suppliers across missions and in all phases of a mission7) disseminate knowledge and promote use of interface for hardware models, especially with hardware vendors 8) grow culture in hardware suppliers for the development of simulation models of their hardware by means of pilot projects

Performance of European processors for space applications have been increasing over the years, from the ERC32 (25MHz, current missions) to the single-core Leon2/3 (100MHz, upcoming missions) to the next generation processor (multicore, Leon4, future missions). Simulators are needed throughout the software, spacecraft and operations development. Simulator performance needs to keep the pace with the processors. Instruction set simulators for the ERC32 could keep up with real-time simulation of the overall spacecraft. Simulators are being upgraded to cope with Leon2/3 using two techniques, hardware-in-the-loop emulation using FPGAs and just-in-time/dynamic-translation/block-oriented software simulation. HIL is operational for flight software and delivers sufficient performance for Leon2/3, while JIT simulators have not been fully demonstrated yet for flight/embedded software for Leon2/3. The next step towards NGMP multicore processors still needs to be taken.Therefore JIT/dynamic-translation/block-oriented emulators for Leon2/3 need to be consolidated and characterised against benchmarks, while software and hardware emulators need to be upgraded and characterised for NGMP next generation multicore processors.Other ways to boost performance is also to simulate the basic software or other layers (e.g. one from Spacecraft Onboard Interface Services (SOIS)) to have purely a functional simulator which can even run on the operating system of a workstation. This is made possible by the on-board software reference architecture that defines a software bus as the interface between the application and the execution platform. It is therefore possible to replace the on-board execution platform (NGMP based) by a conformant Linux based execution platform. This could enable functional validation of application software running over this simulation layer.Also, to shorten development time of simulator developments (Software Validation Facilities, Functional Verification simulators, Operational Simulators) and to avoid that several simulator developers re-develop the same models of the same hardware in different fashions for different simulation platforms, common interfaces should be defined so that hardware suppliers can deliver a functional model of their hardware units along with the units.