The objective of this activity is to demonstrate the feasibility and performance evaluation of an end-to-end process, tools and building blocks from application level specification down to representative implementation of the combination of OnBoard Software Reference Architecture, IMA and multicore.

 

 

The works performed by Savoir-Faire, Savoir-IMA and the related industrial activities have not investigated yet the particular impact of a multicore in the hardware topology on the On-Board Software Reference Architecture. The architectural principles are indeed modular enough to minimize the impacts of the use of a new type of processors. Using a multicore (also in the scope of IMA) in this scope is feasible. But specific aspects need to be investigated:

 

• Insertion of a new hardware concept in the Space Component Model ("core") and its position with respect to a mono-processor or a partition, in particular the relationship partition/core.

 

• Refinement of the notion of deployment of components on cores in addition to partitions.

 

• Impact of multicore on the execution platform, and any possible constraints at component model level. Major impacts are expected in the notion of interpartition or inter-core communication, and on the scheduling of partitions on cores. The determinism of the real-time behaviour of Time partitioning is impacted by a multicore behaviour, as well as data consistency.

 

The activity includes:

 

• Gather the results of the several previous related activities and consolidate them into a synthesis about the theory of the relationship between component model, partitioning and multicore. Among others, analysis of the overheads and lack of determinisms of multicore (and in particular the NGMP) on the Time and Space partitioning concept, analysis of the mapping partition/core (1 to 1, several partition on a core, 1 partition across cores), analysis of the relationship between the component model and partitioning/multicore and viceversa, etc.

 

• Evolution of the Space Component Model (and associated editor tools) to allow the expression of multi-cores in the hardware topology.

 

• Evolution of the execution platform to support TSP and multicore.

 

• Evolution of the tools to deploy the components on multicore hardware with the updated execution platform.

 

• Case study on the Estec avionics test bench using the updated tools and execution platform.