The objective is to study, identify and validate the enabling technologies for future TTC transponders/transceivers, with a main goal to enhance manufacturing and integration of key transponder components towards a System-on-Chip concept which can be used as a core building block in future TTC transponders and transceivers.

 

 

The use of the VLSI technologies (through high density, low power consumption digital ASICs) together with RF miniaturisation techniques (Analogue ASIC, MMIC,System on a chip etc.) are being used in many devices in order to develop lighter and smaller transponders. Particular examples of these are:

 

• The TTC subsystem for the future deep space missions, such as Bepi-Colombo.

 

• Lander and orbiter proximity link transponders/transceivers.

 

• Earth Observation S-band TRSPs.

 

• Telecommunication command receivers, transmitters and beacons.

 

The higher integration at circuit level results in a decrease in the number of required components. This simplifies the integration process and reduces the associated tuning activities. This has significant benefits, both in terms of design robustness and cost reduction.

Higher integration can also be used to include more functions inside the transponder in order to increase its flexibility whilst reducing the unit mass.

 

This activity will provide a critical assessment of the technologies on how to reduce the mass and power consumption of future transponders/tranceivers for use on spacecraft/landers and will manufacture and test a generic system on a chip for use in multiple transponder units for different space applications. This will require the design, development and validation/verification of a highly integrated building block for use in multiple TTC TRSP units and will be tested as part of an integrated breadboard.