DANOE Phase II (High Dynamic Absolute Nanometric Optical Encoder technology assessment for space)

A DANOE encoder breadboard has been built and tested. This second phase aims at:Derive detailed requirements for the DANOE electronic and confirm the functional performances through an Elegant Breadboard passing some preliminary environmental tests.Produce a preliminary design of the Danoe electronic by assessing the imager and terminating with a FPGA SRR.Updating the market survey, the sensor recurrent cost estimation, the cost at QM completion.  

Combining all the features in a position encoder such as high-resolution, absolute, compact, high-speed is a challenge today. An optical absolute position encoder technology has the potential to combine all these attractive features. Nanometric resolution can be established using dedicated optical sensor, a transmissive scale, LED illumination, without the need for optics (shadow-imaging). Optic-less shadowimaging permits compact design and major cost reduction.Coarse absolute position measurement is obtained by decoding the subsection of the Manchester code (typically 8-14 bits), which is seen at a given position by the sensor. Fine relative position measurements is attained by Fourier analysis-like processing of the regular grating. Robustness, precision and very high resolution is guaranteed by heavily oversampling the pattern (typically 8-16 pixels per pattern period) and relying on the phase information which is distributed in the entire image among hundreds or thousands of pixels. The combination of the coarse and the fine measurements yields very high-resolution absolute position, typically 16-30 bits for rotary or linear encoder.A DANOE encoder breadboard has been built and tested. After this development, it is found too early to define a detailed architecture for the DANOE electronic for the following reasons:The calibration methods (on ground, in-flight) are unclear (the various bias influencing the final absolute accuracy are not yet combined in a budget).Despite the core algorithm is existing from CSEM, several filtering methods are still candidate to improve the accuracy.A deep Rad-hard imager and FPGA trade-offs have not been performed.The current breadboard will be upgraded to an Elegant Breadboard in this Phase IIand will pass environmental tests.