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The knowledge bank of ESA’s R&D programmes

Improved Ge wafer technology for multijunction solar cells V

Programme
GSTP
Programme Reference
GT27-098EP
Prime Contractor
UMICORE NV
Start Date
End Date
Status
Closed
Country
Belgium
Improved Ge wafer technology for multijunction solar cells V
Objectives
The proposed activity has four key objectives: to improve the Germanium (Ge) wafers' quality focusing on a better customer yield, to improve the current figures of rejection rate after epitaxial growth, to improve the manufacturing processes aiming at increased internal yield and finally to reduce cost.
Description
The proposed activity will address the improvement of Ge substrates for the growth of advanced triple junction solar cells. The final objective will be the demonstration of the good quality of the wafer at the customers? premises. The proposed activity will enable to maintain the technological leadership while at the same time to keep the cost of the product competitive thanks to best-in-class manufacturing technologies. ;
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Within this activity, the manufacturing processes and the final product will be further optimized so that a maximum of 2% rejection rate, after epitaxial growth, at the customer's premises can be guaranteed. The three main reasons for rejection at customers identified today are: scratches, fried eggs and icebergs. In the course of this activity the occurrence of these defects will be reduced to diminish the wafers rejected after the epitaxial growth, which will have as a consequence a reduction of cost of both wafers and solar cells. In order to achieve this objective the activity will focus on 4 different axes:
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1. Improvement of the inspection methods during manufacturing ;2. Improvement of the polishing steps (surface improvement) 3. Reduction of the pit level (surface improvement) 4. Making every wafer 100% fit for use, by focusing deeper on the correlation between defects after epi versus before epi
Application Domain
Generic Technologies
Technology Domain
3 - Space Systems Electrical Power
Competence Domain
4-Electric Architecture, Power and Energy, EMC
Initial TRL
TRL 3
Target TRL
TRL 7