Flash FPGAs combine the reprogrammability and flexibility of SRAM-based FPGAS, with immunity to configuration upsets, low static power and a non-volatile configuration, which are characteristics more common to antifuse-based FPGAs. The latest developments in Flash-based FPGAs, e.g. the 4th generation Microsemi Flash FPGAs (RTG4), offer a high number of high-performance programmable logic resources, large and fast on-board memories, and high performance I/O - SERDES, LVDS, DDR, etc.

New satellite designs entail more and more complex functionalities implemented in Field Programmable Gate Arrays (FPGA). Although Europe is far behind the US in the availability of powerful FPGAs, the first European reprogrammable radiation hard FPGAs offer the unique opportunity to develop new, larger capacity European ITAR-free FPGAs including the silicon parts, software hardware development and programming tools to be able to cover the big gap.

At present there are few European compact connector solutions that offer performances required for high speed operation of SpaceWire as well as meeting the stringent environmental requirements in space applications. The ECSS E-ST-50-12C defines the connectors and cables to be used on a SpaceWire Cable Assembly, respectively as per ESCC 3401/071 and ESCC 3902/003. Recent developments done under the frame of an ESA TRP activity lead to the definition of new cable variants allowing noticeable mass saving, compared to the current variant of the ESCC 3902/003.

The main tasks will be:-design-Foundry-Test of performances with existing CMOS detectors-Radiation tests

The use of a traditional flat image sensor requires optical elements to project the image onto a flat plane.  Introducing an appropriately curved sensor removes the need for these optical elements. Thus, by eliminating one constraint on the design of the lens it becomes possible to design systems with reduced size and weight and improved performance.

The main goal of this Ariadna study was to determine the radiation hardness of potential future space processors. The AR0 test-chip was used to study the impact of SEUs and SETs on different versions of a hardened processor on UTBB-FDSOI 28nm technology, including DICE flip-flops, and three different hardening level of combinational logic.

The study will be focused on the prototyping of SiC MOS capacitor structures with the main goal to characterise the overall quality and stability of the gate oxide to SiC interface to gate stress as well as the radiation performances of SiC gate oxide in terms of SEE and TID testing.