The objectives of this de-risking phase were to develop a single low-power / high reliability board based on the capabilities of the SmartFusion2 SoC. The developed board was made ready for a future implementation as a warm/hot-redundant OBC with all connections in electronics necessary for the redundancy concept. The RTEMS / NASA cFS software demonstration was created to demonstrate the features of the board with realistic flight software.

Onboard computers (OBCs) are a requirement for every spacecraft, from satellites to rovers. Planetary Transportation Systems (PTS) has taken on the task of developing their own OBC unit in-house, tailored to the company’s needs: the in-house development of CubeSats and cooperative avionics technology, as well as own missions at large scale. The development status was raised to TRL 4 within this de-risking activity. The follow-on developments are planned to reach TRL 6.   

The design was updated to improve the thermal/mechanical design of the board, as well as the electronic design, accommodating the requirements that stem from new intended use-cases. The requirements of the OBC and CM concerning hardware, software, functionality, redundancy and other topics have been defined and analyzed. An emphasis was put on the power demands, storage possibilities and reliability of data to ensure a smooth running of the finalized product. The prototype was built. The case was developed and 3D-printed. The software interface  has been developed. The board and SW applications have been successfully tested in-house and are ready for the next development stage.

The board was originally intended for the use in the company’s ALINA lunar lander and lunar rover in a European Moon Mission. The company’s mid-time goals have shifted since the project was initially presented. The new board design matches the current technology roadmap and promises interesting opportunities for the market and the Agency.

This de-risking effort was planned to kick off and drive the internal development from the concept stage to a usable prototype. The anticipated follow-on development, split in two more stages, will focus, among others, on more functions of the core Onboard Software, TM/TC concept and implementation, memory management, additional bootloader functions and modes and testing, as well as the full implementation and environmental testing of the redundant OBC.