The main objectives of this study were: to appraise existing ESTRACK groundstation receiver anddemodulator equipment; to demonstrate the feasibility of introducing DSP technology up to the 70 MHz I/F interface for next generation receivers; to identify and propose a design architecture;to identify functional modules common to different demodulation types; and to identify criticaltechnical areas that required breadboarding in Phase 2.

The study began with a detailed analysis of the existing ESTRACK groundstation receiver equipment. Concurrently with this, a study was made of high performance DSP components. The conclusion was that there were two processors best suited to this application: the Analog DevicesADSP-21060 SHARC and the Texas Instruments TMS320C40. Of these, the SHARC was the preferred choice.

The balance of the study then concentrated on design analysis, proposed architecture andassessment of algorithms running on this proposed architecture. This resulted in practicalproposals for an all-digital receiver supported by quantitative analysis of algorithm performance.The receiver architecture consisted of a programmable hardware front end plus an array of (atleast six) SHARC processors.

We proposed two main areas that warrantedbreadboarding: the analogue input and parallel algorithm implementation. A third breadboarding activity, to develop a prototype programmable front end, was presented as an additional cost option.

In summary, we proposed a programmable digital solution for the next generation ESTRACK groundstation receiver/demodulator. We demonstrated that this solution both met ESA requirements and was technically feasible. The next step was to breadboard key parts of theproposed design in order to reduce development risk and to provide a firm basis for a planneddevelopment and build program.