In the framework of the on-board payload data processing reference system, the computing power is de-centralised and distributed in well-defined processing modules where the applications rely on. One of the major benefits of this architecture is to allow the independent technological evolution of the modules without affecting the architecture itself: objective of this activity is therefore to provide the system with new processing models that can be, on one side, painless inserted into the exiting architecture and, on the other side, not specifically designed for a particular need. In this way, words like equipment re-use or non-recurrent costs saving become realistic; but which hardware components can we use for such a development? The most profitable solution is to develop this processing module using an FPGA based design: this approach gives some flexibility during the definition and early validation phase as well as smooth porting of the demonstration to its flight version (using space qualified FPGAs).