Nebula Public Library

The knowledge bank of ESA’s R&D programmes

Modelling of Spacewire Networks

Programme Reference
Prime Contractor
Start Date
End Date
Upgrade of the ESA MOST tool box to
  • Implement models of additional SpaceWire components.
  • Add Hardware-In-The-Loop simulation capability.
  • Raise the TRL from 3 (Alpha version) to 4 (Beta version) through test and cross-validation with SpaceWire hardware.
After more than 15 years of development at international level lead by ESA, SpaceWire has become the workhorse for high data rate on-board communications, not only for ESA missions but for other space agencies (NASA, JAXA, ROSCOSMOS) and for the space industry. This technology has become a de facto standard for payload systems and is now being used for avionics. The capability provided by SpaceWire to develop data handling systems based on high-speed networks rather than low-speed buses allows much greater performance but implies mastering much more complex communication schemes. This can only partially be done through analysis and the SpaceWire and On-Board Data Handling communities have expressed the need for a SpaceWire traffic simulator.
From 2010 to 2014, ESA has developed through TRP funding a tool allowing simulation of SpaceWire traffic. The tool, still in development, was used for analysis of BepiColombo and MTG traffics as well as for Metop-SG pre-design phase. MOST raised great interest from primes. The community of SpaceWire users expressed high interest for this tool presented and demonstrated many times even before its first release in Q2 2013.
Although the first MOST (v2.2) release is very welcome by major system integrators and by the SpaceWire community for its usefulness, it is still incomplete:
  • A number of SpaceWire-enabled components just being developed or already flying (e.g. SpW-SMCS-116, SpW-SMCS-332, RTC, etc) are not modelled yet. These features are requested by SpaceWire users.
  • To troubleshoot spacecraft breadboard/EM (?flat sat?) SpaceWire networks, Harware-In-The-Loop simulation capability is required.
  • Users are also requesting that the TRL be raised from ?Alpha version? (SW TRL from 3) to ?Beta version? (SW TRL 4).
As part of the development of MOST v2.2, additional features have been identified that are requested by the SpaceWire users and are perfectly achievable in the current framework, i.e. MOST and OpNet (TM) Modeler?.
The answer to the need is straightforward: develop the MOST models of SpaceWire-enabled devices that have been identified as missing and useful; add Harware-In-The-Loop simulation capability; raise the TRL from 3 (Alpha version) to (Beta version) through test and cross-validation with SpaceWire hardware.
The tasks related to this activity are then:
  • Development of MOST models for a number of SpaceWire-enabled devices:
  • Detailed specification the models selected for development.
  • Implementation of the specified models.
  • Verification (test) the implemented models
  • Validation of the set of additional models through cross-validation with SpaceWire hardware:
  • Detailed specification the validation scenarios.
  • Detailed design the validation scenarios.
  • Implementation of the validation scenarios.
  • Validation of the implemented models through cross-validation with SpaceWire hardware.
  • Addition of Hardware-In-The-Loop simulation capability:
  • Detailed specification the Hardware-In-The-Loop simulation capability.
  • Detailed design the Hardware-In-The-Loop simulation capability.
  • Implementation of the Hardware-In-The-Loop simulation capability.
  • Demonstration of the Hardware-In-The-Loop simulation capability.
Application Domain
Generic Technologies
Technology Domain
1 - On-board Data Subsystems
Competence Domain
3-Avionic Systems
Initial TRL
Target TRL
Public Document
Executive Summary