The proposed activity will prototype SPI protocol(s) and physical layers for space applications.

The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link de facto standard, named by Motorola, that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Based on the result of two running TEC-EDD activities (Modular RTU - GSTP, Standardization of Digital interfaces - TRP) this activity will prototype SPI protocol(s) and physical layers for space applications. A demonstrator will be built and it will be flexible in order to simulate all the conceivable scenarios : SPI as internal backplane bus inside an unit , SPI as serial bus for reprogrammable logic on board (FPGA, NVRAM, ...), SPI as interface with sensors ( e.g. contactless angular sensors, ...), SPI as interface for new ICs to be developed (Wireless Analogue Radio, ADC/DAC, ...). Signal integrity techniques as parity bit, replication or triplication of messages at level of protocol and also improvement of the physical layer ( e.g. adoption of LVDS differential signalling for intra-unit data communication) will be investigated and prototyped. Test Reports, recommendations ( Technical Note) and material for website will be produced.