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De-risk assessment: HERA IP-ICU (Image Processing Interface Control Unit)

Programme Reference
Prime Contractor
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End Date
De-risk assessment: HERA IP-ICU (Image Processing   Interface Control Unit)

Objective(s): The activity included a pre-development targeting the HERA mission and aimed at achieving an avionics hardware platform for the Image Processing Board and Interface Control Unit hardware equipment for HERA mission up to Elegant Breadboard TRL 5.

The development is based on a dual-purpose avionics processing board for the Image Processing Unit and combined Interfaces Control Unit (IP-ICU). The scope of the project encompassed a skeleton implementation of the breadboard model, not including high level implementation of TM/TC Data Handling and neither the needed Image Processing implementation in the FPGA.


Background and justification: The hardware development IP-ICU is foreseen with direct and immediate applicability to ESA HERA mission. It has been identified under HERA Phase A/B1 development work there is a lack of processing component capable to execute the required vision-based algorithms, during the different mission phases. An analysis has been performed on possible implementations and the result showed the necessity for a dedicated FPGA for the implementation of Image Processing part as central part of the unit.

Achievements and status: IP-ICU EBB is a TRL 5  avionics equipment tailored for HERA mission and completely in line with the mission needs in terms of functionality, interfaces and processing capabilities. The unit was designed taking into account flexibility for migration to higher TRLs.

The power tree was carefully designed and validated by means of a separate dedicated implementation IP-ICU PSU BB (Power Suply Unit Breadboard), prior to IP-ICU EBB manufacturing.

The equipment was successfully designed and validated by GMV, as skeleton unit.

IP-ICU provides 2 SpaceWire Interfaces allowing a data rates up to 92 Mbps. The architectures includes 2 separate FPGAs for separation of data handling and image processing functionalities (NanoXplore NG-Medium and Xilinx Virtex-5), and reconfigurability of the FPGA assigned for processing (Virtex-5).

Benefits: IP-ICU has a very high potential for being adapted to different space missions as both versatile image processing board and hub for multiple space representative data interfaces. A wider variety of missions employing vision based navigation would benefit from the development, ranging from space exploration (asteroid characterization, planetary landing, sample return) to on orbit servicing and active debris removal.

Application Domain
Generic Technologies
Technology Domain
1 - On-board Data Subsystems
Competence Domain
9-Digital Engineering
Initial TRL
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Public Document
Final Presentation
Executive Summary