The Compact Reconfigurable Avionics activity aims at providing a flexible solution for small spacecrafts (typically 150 - 500 kg) allowing reducing the size of their Avionics (Data Handling Core and smart AOCS elements) while fulfilling hi-performance and defined reliability requirements. Within this frame, the objective of the Reconfigurable Data Handling Core development is to design and manufacture a module hosting a high performance microprocessor and high capacity reconfigurable FPGAs. The module will support standardised interfaces (Mil1553B, CAN, SpaceWire) and lower level digital interfaces (sensor buses) used natively or as a bridge to Analog interface devices. This module acts as the execution platform for the Compact Reconfigurable Avionics cross sectorial activity.

The general approach while designing a Reconfigurable Avionics will follow the general principles: - Implementing by default most of the functions as SW - Using (slave) reprogrammable FPGA(s) as an accelerator to implement too CPU intensive functions - Providing a scalable and versatile I/O system supported by flexible SW drivers - Extending digital I/Os by Analogue Front-ends The selected hardware platform is the combination of a powerful microprocessor and one or several high-end reconfigurable FPGAs, fulfilling the following needs: - Supporting exploratory and evolutionary designs according to mission needs during early development phases. The advantage at this stage is clearly to reduce costs thanks to using a flight representative and stable hardware platform based on SW defined functions off-loaded when required by blocks implemented in reprogrammable FPGAs - Allowing in-flight reconfigurations for the adaptation to different mission phases and modes. For instance, processing algorithms can be tuned according to evolving needs (science mission) or re-defined during the execution of the mission (e.g. for active de-orbiting). - Enabling a mission recuse in case of FDIR events or failures that could be rescued by a deep reconfiguration or the spacecraft core functions. The activity consists in developing at EBB level a HW module hosting a high end microprocessor, FPGAs and corresponding support equipment. A selection of IP Cores taken from ESA's portfolio will be implemented and validated on the target. Eventually the Reconfigurable Data Handling core shall be part of the Compact Reconfigurable Avionics test bench installed in ESTEC's Avionics Lab.