The objectives of the proposed activity are the definition, design and breadboarding of the avionics for Proba-Next (small) platform for IOD related to the power management, the data handling and the mass memory.

 

 

In the frame of the GSTP program, an activity called Advanced Data and Power Management System (ADPMS) was initiated in 2000. This activity had the objective to develop advanced combined power management and data handling in a single box targeting Proba like small platforms. The activity resulted in the complete design of the core of the Proba platform avionics and was produced in flight models for Proba-2 and Proba-V. Both satellites are now in orbit and are cumulating more than 5 years of operations. The ESA IXV mission has also selected ADPMS for its on-board computer, the flight model has been delivered to IXV Prime. The baseline for the future Proba-3 satellites and the commercial VNREDSAT-1B has selected ADPMS for their avionics.

 

Also in the frame of the GSTP program and to support to future In-Orbit Demonstration missions, the Proba-Next activity was initiated in September 2013 with the objective to study the evolution of present Proba platform based on the experience gained with Proba-1, Proba-2 and Proba-V. The activity is divided into 2 main phases. The first phase is dedicated to identification of necessary changes to the Proba platform to improve its performances in all aspects including the addition of propulsion and to reduce its recurrent cost. The second phase is dedicated to study the Altius mission and further design the Proba-Next platform for the target mission up to a phase B level for the platform.

 

Proba-Next has now completed the phase 1 reaching the Mid Term Review (MTR), with the identification of the necessity to evolve its avionics (i.e. ADPMS) to reduce its production time, its recurrent cost, to increase its capabilities in terms of power handling, in processing performances and mass memory capacity.

 

The activity proposed will, on the experience gained with the Proba platform and the available building blocks of the present ADPMS design, study, design and bread-board the evolution of avionics for the Proba-Next platform.

 

The study will start from the outcome of the Proba-Next phase 1 and will define the major drivers and the baseline architecture of the Proba-Next avionics. It will follow common Space Avionics Open Interface Architecture (SAVOIR) initiative in which the approach based on reference architectures and building blocks plays a key role. The architecture of the avionics will as for ADPMS cover the power management, the data handling and the mass memory platform functions. From the start of the activity the reduction of the recurring cost and production time will be a major driver to architecture selection. The development will be established at this stage of the activity.

 

The design phase of the activity will revisit the existing building blocks and adapt their detailed design to the proposed architecture. The new building blocks will be detailed design up to schematic level. A new mechanical accommodation of the ADPMS will to be designed to fit with the requirements of the Proba-Next platform.

 

The main design drivers are:

 

• Power distribution up to 450W, compared to 300W in the present ADPMS.

 

• Processing performance up to 200MIPS compared to the present 80 MIPS.

 

 

• Permanent mass memory of 300GBit compared to 100GBit at the moment.

 

• The objective will be to keep the same ADPMS mass (below 15kg) and volume (below 20dm3).

 

• The design will need to sustain space environment for mission in low and medium earth orbits.

 

In order to achieve the above objectives, state of art components will need to surveyed and selected during the design phase. It has already been identified that a System On Chip (based on LEON-3) will be the core of the data processing.

 

Finally, the activity will breadboard the main cores of the future Proba-Next Avionics with the aim to reduce this (elegant) breadboard in the future Proba-Next avionics engineering model:

 

• The processor, telemetry/telecommand and the reconfiguration modules.

 

• The power distribution and conditioning modules.

 

• The mass memory elementary module.