Time-to-Digital Converters (TDCs) are crucial elements in many sensor readout systems, such as time-of-flight sensors, laser ranging devices, LiDAR, ultrasonic sensors, particle detectors, etc. To the best of our knowledge, there is currently no rad-hard TDC component available on the market, which could meet the targeted specification defined in this project. The goal of this project is prototyping and lab testing of a radiation-hardened single-chip picosecond TDC in a commercial 65 nm CMOS technology. The TDC will be able to measure time differences between a start and stop signal and convert this to a digital value with an accuracy better than 10 picoseconds. It will support ‘single shot’ operation, which means it can carry out the conversion with the proposed accuracy even from a single start and stop signal, without averaging or noise shaping. Innovation content of this project has focused on the following aspects: 1. Current radiation tolerant TDCs are mostly based on radiation tolerant FPGAs with a resolution of around 100 ps and radiation tolerance up to merely 10 kGy. FPGA based TDCs suffer from high power consumption, high implementation cost, large device size, and limited resolution. The TDC proposed in this project will be implemented in a mainstream commercial 65 nm CMOS process, which offers highest integration level, lowest power consumption, and lower fabrication cost for volume production. 2. For this circuit, a Total Ionizing Dose (TID) tolerance of 100 kGy, and a SEE tolerance up to a Linear Energy Transfer (LET) of 100 MeV/mg.cm2 is targeted. These requirements are in line with the most extreme environments encountered in space. 3. It has been shown that ionizing radiation causes changes in transistor parameters, increases 1/f noise and worsens mismatch problems. Especially the latter two effects have a huge impact on the accuracy of TDCs. In this project, innovations will be proposed to achieve sub-10 ps performance in the presence of TID and SEE.