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Securing NG-Ultra FPGA development through innovative System-on-a-Chip (SoC) validation

Sat, 11/12/2022 - 02:01
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The objective of the activity is to perform activities that will minimize functionality risks of the System-on-a-Chip (SoC) part in the NG-ULTRA final product. The activities will reinforce the validation of the SoC and support its integration.
The BRAVE series of reprogrammable FPGA’s represent an entirely new area of development for microelectronics. These high performance, very advanced electronics could revolutionise the manufacturing process and performance of multiple missions. Alongside their development there is a current industry initiative to standardise avionics systems. As part of this venture, GSTP Element 2 has initiated an activity to develop a standardised box, which will contain all the different computer modules, such as power boards, and ensure they are all compatible. This activity is expected to be one of the first onboard computers to use the BRAVE Ultra FPGA technology, and will certainly be the first in Europe.
More and more complex functionalities are implemented in Field Programmable Gate Arrays (FPGA). The BRAVE FPGAs is a European family of FPGAs to cover a range of needs in the development of space units/ equipment. The current family is composed of three products that are at different stage: ;NG-MEDIUM (already available and at advanced qualification stage), NG-LARGE (prototypes available in Sept. 2019) and the NG-ULTRA in FD-SOI (Fully Depleted Silicon On Insulator) 28nm technology.
The NG-ULTRA FPGA, currently being developed by NanoXplore (FR), has many advantages compared to the current space FPGA's state-of-the-art. To start, using FD-SOI 28nm technology presents the advantage of higher integration, higher performance, lower power consumption and requires less effort to adapt it to radiation environments. Another important factor is the architectural advantage, as it includes in the same component both, the FPGA part (PL, Programmable Logic), and the System-on-Chip part (PS, Processor System).
The NG-ULTRA SoC part is currently under development. Due to its high complexity, functional risks have been identified that require the following design and validation task:
    • SoC design consolidation and support to the integration in the NG-ULTRA FPGA. Finalize the detail conception of the SoC mainly by completing the design architectural optimization, include the Design For Test (DFT) in the SoC design and finalize the design to reach the final database to be delivered and integrated to the NG-ULTRA FPGA.
    • Validation in hardware: The functionality is also validated in 2 platforms: the initial FPGA-based board, which has limitations, and the new approach using the ASIC emulator.

The above activities will be performed by the proposed companies, in support to NanaXplore, since both companies are target customers of the NG-Ultra FPGA.
Application Domain: 
Generic Technologies
Technology Domain: 
23 - Electrical, Electronic and Electro-mechanical (EEE) Components and Quality
Competence Domain: 
3-Avionic Systems
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