In recent years, research in the space community has shown a growing interest in AI, mostly driven by systems miniaturization and commercial competition [1]. FPGAs have proven to be competitive accelerators for these algorithms and works proposing methods for automating the design on these devices have acquired relevance [2]. The common purpose is to enable a wide range of users without specific skills to accelerate AI models on FPGAs with reduced development times. Among the emerging frameworks, FPG-AI constitutes a valuable option for promoting the deployment of AI onboard the satellite. The foundations (TRL2) of this toolflow have been developed with a previous research activity between ESA and the University of Pisa [3].

Unlike other solutions, FPG-AI is not a vendor-specific flow and does not pose technology limits on the characterization (inference time, resources, power) of AI accelerators. In addition, the framework features a fully-handcrafted and human-readable HDL with no third-party IPs, thus facilitating code explicability, reliability, and space qualification. FPG-AI provides as output the HDL sources of the accelerator and not the final bitstream, allowing the user to exploit the unused portion of the FPGA for complementary tasks. The main objectives of this project are to reach TRL4 of FPG-AI and make it available to the space community.

This will be done by:

• Extending and consolidating the framework to a wider set of supported AI algorithms, e.g. Recurrent Neural Networks (RNNs), providing hardware characterization of AI-based space applications such as FDIR or Telemetry Forecasting.
• Ensuring that all state-of-the-art devices are supported by the tool, especially focusing NanoXplore FPGAs, enabling the use of these devices for AI applications and pursuing European sovereignty.
• Evaluating the tool capability with a prototype hardware demonstrator. ​This idea has already gained interest from industry (NanoXplore,Thales,Sitael,IngeniArs,Aiko).

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