Development of an Intellectual Property (IP) core for a complete SpaceWire node interface

The SpaceWire codec IP cores offered by ESA's IP core service are widely used many projects. Other important functions of a SpaceWire interface like time counter, configuration port and hardware support for protocols have still to be designed by the user. This work requires still in depth knowledge of the SpaceWire standard which is often not the focus of a scientist developing an instrument. The SpaceWire node interface IP core shall provide an easy access to SpaceWire where all mandatory features are implemented in a standard compliant way. This configurable SpaceWire node IP core shall integrate a number of existing IP cores like the SpaceWire coded, Remote Access Memory Protocol (RMAP) IP core and complement them by adding the configuration port zero, inter port routing, time counter, scheduled traffic control, SpaceWire-D and PnP protocol support. Parameters like the number of SpaceWire links, the level of support for the different protocols in hardware and the type of on chip interface shall be easily configurable for every instantiation of this IP core. This IP core shall be prototyped and validated using a demonstrator in FPGA technology.