Quality Assessment of the new European Large BRAVE FPGA Software Tools (Queens)
Programme
                            TDE
            Programme Reference
                            T725-601QQ
            Prime Contractor
                            GMV AEROSPACE AND DEFENCE, SA
            Start Date
                            End Date
                            Status
                            Closed
            Country
                            Spain
             
          Objectives
                            To demonstrate the capability of the Large Brave FPGA fpgas software tools to program and validate the devices
Description
                            FPGA are increasingly being used to implement complex and critical functions on-board satellites at both platform and payload level, for a diverse range of applications, including: micro-controller processors, data compression, image data processing and others. The new European Space BRAVE FPGA is being developed in various sizes and offering various complex functionality. Their software tool chain is intended for use in the end-to-end FPGA Development Lifecycle to ensure devices are correctly programmed, starting from the functional specification of the device behaviour through to the final verification and validation in the target environment. It is clear that new software tools used in this process are fundamental to achieving the quality objectives of the programmed devices for flight. This end-to-end process to program and validate the custom devices often relies on proprietary tools that are not subject to a specific qualification exercise.
This drove defining and applying a Methodology to assess these tools, from a Quality perspective, for the BRAVE Medium FPGA (T725-502QQ ?Quality Assessment of the new European Space FPGA Software Tools?. Riding from the success achieved for the BRAVE Medium FPGA tools, there is a need to extend this activity to the BRAVE Large (NG-LARGE) FPGA tools, which includes ARM R5 platform and High Speed Serial Link (SERDES).
Tasks:
- review approach and methodology
- assess SW Quality of new European Space medium FPGA end-to-end tool chain
- Apply this improved methodology and approach within the new European Space FPGA end to end FPGA Software Tool Chain. This will ensure that the tools are fit for their purpose and can evolve for future releases maintaining the Quality level.
An important part of this phase will involve a Proof of Concept Demonstration based on the tool user manuals and Bench Marks obtained from test vehicles and ESA/Third Party IP Cores. This will be based on specific Use Cases provided by ESA, as elements of an ESA portfolio of IP Cores.
Application Domain
                            Generic Technologies
            Technology Domain
                            25 - Quality, Dependability and Safety
            Competence Domain
                            1-EEE Components, Photonics, MEMS
            Initial TRL
                            TRL 2
            Target TRL
                            TRL 4
            Achieved TRL
                            TRL 4
            Public Document
                            Executive Summary
      
            
      
      