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Quality Assessment of the new European Ultra BRAVE FPGA Software Tools (Queens3)

Programme
TDE
Programme Reference
T725-705QQ
Prime Contractor
GMV AEROSPACE AND DEFENCE, SA
Start Date
End Date
Status
Closed
Country
Spain
Objectives

Define methodology to provide quality assessment of the BRAVE Ultra Software tools, apply methodology for specific use cases, report findings and upgrade tools accordingly

Description
FPGA are increasingly being used to implement complex and critical functions on-board satellites at both platform and payload level, for a diverse range of applications, including: micro-controller processors, data compression, image data processing and others. ;;The qualification of these programmed devices for use in space is based on an exhaustive Verification and Validation process that attempts to exercise a large set of Test Vectors to ensure that the device functionality, error handling and performance are correct. This end to end process to program and validate the custom devices often relies on proprietary tools that are not subject to a specific qualification exercise. ;The new European Space BRAVE FPGA is being developed in various sizes and offering various complex functionality. This has driven definition and application of a Methodology to assess these tools, from a quality perspective, for the BRAVE Medium FPGA (T725-502QQ) and the BRAVE Large FPGA (T725-601QQ). ;The BRAVE Ultra FPGA offers new functionalities at the expense of higher level of complexity especially the interface between the quad-core ARM Cortex-R5 SoC and the FPGA part. Based on the success of the previous activities, there is a need to extend this work to the BRAVE Ultra FPGA. ;;This activity encompasses the following tasks: - Review the approach and methodology which was defined to assess the SW Quality of the new European Space medium/large FPGA end-to-end Tool Chain; ;- Expand the definition for the new functionalities and extended complexity of BRAVE Ultra FPGA,by assessing the S/W tools development, validation and maintenance including configuration control - Define the procurement of Third Party FPGA IP Core ( e.g. SpaceWire, SpaceFiber, CAN) as a use case. - Apply the improved methodology and approach within the BRAVE ULTRAFPGA end to end Software Tool Chain. This will ensure that the tools are fit for their purpose and can evolve for future releases maintaining the Quality level. ;An important part of this phase will involve a Proof of Concept Demonstration based on the tool user manuals and Benchmarks obtained from test vehicles and ESA/Third Party IP Cores. This will be based on specific Use Cases provided by ESA, as elements of an ESA portfolio of IP Cores.
Application Domain
GEN-Generic Technologies
Technology Domain
25-Quality, Dependability and Safety
Competence Domain
1-EEE Components, Photonics, MEMS
Initial TRL
TRL 2
Target TRL
TRL 4
Achieved TRL
TRL 4